
	copy .\out_rtl\define.v .\
	vlib work
	vlog -reportprogress 30 -work work .\out_rtl\define.v
	vlog -reportprogress 30 -work work .\out_rtl\bench.v
	vlog -reportprogress 30 -work work .\out_rtl\clkgen.v
	vlog -reportprogress 30 -work work .\out_rtl\dmem.v
	vlog -reportprogress 30 -work work .\out_rtl\pmem.v
	vlog -reportprogress 30 -work work .\out_rtl\mangyun.v
	vsim -c -do .\out_rtl\wave.do work.bench

